LC-VCO design optimization methodology based on the gm/ID ratio for nanometer CMOS technologies

In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier

Offset-calibration with Time-Domain Comparators Using Inversion-mode Varactors

This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit SAR-ADC. The design, fabricated in a 0.18μm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N0001414135

Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation

This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5 GHz and 5.3 GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.Ministerio de Economía y Competitividad TEC2011-2830

Semi-empirical model of MOST and passive devices focused on narrowband RF blocks

This paper presents a semi-empirical modeling of MOST and passive elements to be used in narrowband radiofrequency blocks for nanometer technologies. This model is based on a small set of look-up tables (LUTs) obtained via electrical simulations. The MOST description is valid for all-inversion regions of MOST and the data is extracted as function of the gm=ID characteristic; for the passive devices the LUTs include a simplified model of the element and its principal parasitic at the working frequency f0. These semi-empirical models are validated by designing a set of 2.4-GHz LNAs and 2.4-GHz and 5-GHz VCOs in three different MOST inversion regions

A Sub-µW Reconfigurable Front-End for Invasive Neural Recording

This paper presents a sub-μW ac-coupled reconfigurable front-end for the purpose of neural recording. The proposed topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180 nm CMOS process draws a maximum of 815 nW from a 1 V source. The measured input-referred spot-noise at 500 Hz is 75 nV/√Hz while the integrated noise in the 200 Hz - 5 kHz band is 4.1 μVrms.Ministerio de Economía y Competitividad TEC2016-80923- PJunta de Andalucía TIC 233

Design and power optimization of CMOS RF Blocks operating in the moderate inversion region

PostprintIn this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier design tool is presented. This tool shows that it exists an optimum in the power consumption for a given gain. Different technologies are compared, using the proposed tool, regarding its performance in terms of gain and power consumption in the design space I D -g m /I D . The frequency limit of the applied transistor model is discussed and comparisons with simulations using BSIM3v3 are presented. Implementation of a power amplifier and a VCO at 910MHz in 0.35μm CMOS technology and experimental results are also show

Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors

Postprint. Trabajo presentado en IEEE International Symposium on Circuits and Systems, 2004In this paper the series-parallel association of transistors applied to current mirrors with a non-unity copy factor is studied with regard to mismatch. This technique has been demonstrated to be a valuable tool in the design of low-offset oriented analog circuits. Some measurements are presented as well as a minimum offset design

A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation

This paper describes a multichannel bidirectional front-end for implantable closed-loop neuromodulation. Stimulation artefacts are reduced by way of a 4-channel H-bridge current source sharing stimulator front-end that minimizes residual charge drops in the electrodes via topology-inherent charge balancing. A 4-channel chopper front-end is capable of multichannel recording in the presence of artefacts as a result of its high total common-mode rejection ratio (TCMRR) that accounts for CMRR degradation due to electrode mismatch. Experimental verification of a prototype fabricated in a standard 180 nm process shows a stimulator front-end with 0.059% charge balance and 0.275 nA DC current error. The recording front-end consumes 3.24 µW, tolerates common-mode interference up to 1 Vpp and shows a TCMRR > 66 dB for 500 mVpp inputs.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N00014111031

A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications

This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2nW at 4kS/s and achieves 9.5 ENOB.Ministerio de Economía y Competitividad TEC2012-33634Office of Naval Research (USA) N0001414135